NDLI: Wafer-scale microdevice transfer/interconnect: its application in an AFM-based data-storage system

Content Provider	IEEE Xplore Digital Library
Author	Despont, M. Drechsler, U. Yu, R. Pogge, H.B. Vettiger, P.
Copyright Year	1992
Abstract	We have developed a robust, CMOS back end of the line (BEOL) compatible, wafer-scale device transfer, and interconnect method for batch fabricating systems on chip that are especially suitable for MEMS or VLSI-MEMS applications. We have applied this method to transfer arrays of 4096 free-standing cantilevers with good cantilever flatness control and high-density vertical electrical interconnects to the receiver wafer (typically CMOS). Such an array is used in a highly parallel, scanning-probe-based data-storage system, which we internally call "millipede." A very high-integration density has been achieved, even for wafer-scale transfer, thanks to the interlocking nature of the interconnect structure, which provides easy alignment with an accuracy of 2 /spl mu/m. The typical integration density is 100 cantilevers/mm/sup 2/ and 300 electrical interconnects/mm/sup 2/. Note that only the cantilevers, not a chip with cantilevers, are transferred and, unlike flip-chip technology, our method preserves the device orientation, which is crucial for MEMS applications, where often the MEMS device should have access to its environment (in our case, the cantilever tips are in contact with the storage medium). After device transfer, the system is mechanically and electrically stable up to at least 500/spl deg/C, allowing post-transfer wafer processing.
Sponsorship	IEEE Electron Devices Society American Society of Mechanical Engineering (ASME)
Starting Page	895
Ending Page	901
Page Count	7
File Size	1842725
File Format	PDF
ISSN	10577157
Volume Number	13
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology System-on-a-chip Micromechanical devices Packaging Costs Microelectronics Optical device fabrication Robustness Microelectromechanical devices Contacts wafer-scale 3-D integration Heterogeneous device integration probe-based storage device system on chip (SOC) vertical high-density interconnect
Content Type	Text
Resource Type	Article
Subject	Mechanical Engineering Electrical and Electronic Engineering

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