NDLI: Multidimensional rational approximations with an application to linear transforms

Content Provider	IEEE Xplore Digital Library
Author	Trelewicz, J.Q. Trenary, T.J.
Copyright Year	1991
Abstract	We discuss two new algorithms for the calculation of simultaneous rational approximations with specific computational characteristics. These approximations are used for efficient calculation of linear transforms. We develop an application in compression using the discrete cosine transform (DCT); however, the methods are also applicable to other integer transforms. To facilitate efficient multiplierless implementation for small field programmable gate arrays (FPGAs) or other low-cost processing elements, the rational approximations must have controlled precision (bits), and the numerators must use a minimum number of adds and shifts over the coefficient vector (minimum "length" representation). Our first method uses successive approximation of the coefficients in a suboptimal algorithm with low computational complexity to achieve low-length representations. The convergence of this method is analyzed, along with the closeness of the approximations. The suitability of this method for computational implementation, along with the quality of its representations, are evaluated in the context of continued fraction algorithms. The method is shown to be suitable for real-time computation for algorithms such as JPEG-2000. The second method, which finds the lowest length representation, requires more computation but is tractable for offline computation. This method employs search tree pruning and provides a lower bound for the representation length at each iteration. The computational complexity of this method is analyzed and compared with experimental results.
Sponsorship	IEEE Signal Processing Society
Starting Page	1343
Ending Page	1351
Page Count	9
File Size	309876
File Format	PDF
ISSN	1053587X
Volume Number	52
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multidimensional systems Signal processing algorithms Discrete cosine transforms Field programmable gate arrays Microprocessors Discrete transforms Hardware Computational complexity Application specific integrated circuits Digital signal processing
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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