NDLI: A 100/spl times/100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding

Content Provider	IEEE Xplore Digital Library
Author	Barbaro, M. Burgi, P.-Y. Mortara, A. Nussbaum, P. Heitger, F.
Copyright Year	1966
Abstract	A 100/spl times/100 pixel analog very large scale integration retina is proposed to extract the magnitude and direction of spatial gradients contained in sensed images. The retina implements in a massively parallel fashion, at pixel level, an algorithm based on the concept of steerable filters to compute the gradients. An output rate of up to 1000 frames per second is achieved in a standard CMOS 0.5 /spl mu/m process. The retina provides address-event coded output on two asynchronous buses, one dedicated to the the gradient's direction and another to the gradient's magnitude. The gradient information is temporally ordered from the largest to the smallest gradient's magnitude. Rationales for such an order are borrowed from information theory. Precise timing of the address events is controlled by a decreasing threshold function, whose slope can be dynamically modified to regulate the data flow on the communication bus so as to reduce the number of collisions. Quantitative experimental results from a fully functional silicon demonstrator are presented.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	160
Ending Page	172
Page Count	13
File Size	364276
File Format	PDF
ISSN	00189200
Volume Number	37
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Retina Pixel Very large scale integration Filters Concurrent computing CMOS image sensors CMOS process Information theory Timing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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