NDLI: Silicon on sapphire CMOS for optoelectronic microsystems

Please wait, while we are loading the content...

Silicon on sapphire CMOS for optoelectronic microsystems

Content Provider	IEEE Xplore Digital Library
Author	Andreou, A.G. Kalayjian, Z.K. Apsel, A. Pouliquen, P.O. Athale, R.A. Simonis, G. Reedy, R.
Copyright Year	2001
Description	we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of silicon on sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk silicon CMOS technologies. In the bulk silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of silicon-on-sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues.
Starting Page	22
Ending Page	30
Page Count	9
File Size	420832
File Format	PDF
ISSN	1531636X
Volume Number	1
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon CMOS technology Optical interconnections High speed optical techniques CMOS process Thermal conductivity Very large scale integration Electronics packaging Vertical cavity surface emitting lasers Integrated optics
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optoelectronic-VLSI: photonics integrated with VLSI circuits

A method for improved VCSEL packaging using MEMS and ink-jet technologies

Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits

Progress in Low-Power Switched Optical Interconnects

Performance constraints for onchip optical interconnects

Integrated Silicon PIN Photodiodes Using Deep N-Well in a Standard 0.18-$mu$ m CMOS Technology

A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology

256-channel bidirectional optical interconnect using VCSELs and photodiodes on CMOS

Optoelectronic interconnection technology in the HOLMS system

Silicon on sapphire CMOS for optoelectronic microsystems

Similar Documents

Optoelectronic-VLSI: photonics integrated with VLSI circuits

A method for improved VCSEL packaging using MEMS and ink-jet technologies

Vertical-cavity surface-emitting lasers flip-chip bonded to gigabit-per-second CMOS circuits

Progress in Low-Power Switched Optical Interconnects

Performance constraints for onchip optical interconnects

Integrated Silicon PIN Photodiodes Using Deep N-Well in a Standard 0.18-$mu$ m CMOS Technology

A 36-channel parallel optical interconnect module based on optoelectronics-on-VLSI technology

256-channel bidirectional optical interconnect using VCSELs and photodiodes on CMOS

Optoelectronic interconnection technology in the HOLMS system

Silicon on sapphire CMOS for optoelectronic microsystems