NDLI: Analysis and design of high-speed and low-power CMOS PLAs

Content Provider	IEEE Xplore Digital Library
Author	Jinn-Shyan Wang Ching-Rong Chang Chingwei Yeh
Copyright Year	1966
Abstract	The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Operating behaviors of several conventional PLAs are analyzed first to find out their speed and power bottlenecks. Then, new circuit design techniques for the CMOS PLA are proposed in the hopes of fulfilling the requirements of high speed and low power at the same time. Finally, high speed is achieved through the combined effect of utilization of a fast pseudofootless dynamic circuit and a reduced interplane clock delay. On the other hand, low power is achieved because the power consumption from the three main sources, i.e., the AND-plane circuits, the interplane buffers, and the OR-plane circuits, can be reduced significantly and simultaneously. The delay time and the power consumption of the critical path of a PLA are taken as the performance evaluation parameters. When the 50/spl times/50/spl times/64 PLAs are designed in a 0.35-/spl mu/m 1P4M CMOS technology, the maximum operating frequency of the proposed PLA is 1.61 times higher than that of the fastest conventional PLA. Furthermore, power reduction can be as high as 18% and 43% when the operating frequencies are set to be 100 MHz and 50 MHz, respectively, as compared to the most power-efficient conventional PLA.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1250
Ending Page	1262
Page Count	13
File Size	423677
File Format	PDF
ISSN	00189200
Volume Number	36
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programmable logic arrays CMOS technology Delay effects Energy consumption Frequency CMOS logic circuits Logic circuits Buildings Very large scale integration Circuit synthesis
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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