NDLI: Design of fault-diagnosable and repairable folded PLAs for yield enhancement

Content Provider	IEEE Xplore Digital Library
Author	Wey, C.-L. Chang, T.-Y. Ding, J.
Copyright Year	1966
Abstract	A defect-tolerant PLA (programmable logic array) design with a simple column folding technique to enhance the probe yield is presented. The results show that the design requires less die size than a previous design, while still achieving full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults. The design concept is readily extended to other folding techniques. Among the various folding techniques, the trade-offs are the density improvement and regularity, i.e. the density improvement is often paid for as higher irregularity. In fact, the irregularity often results in a higher defect density. It is concluded that a density improvement does not guarantee a higher overall yield.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	54
Ending Page	57
Page Count	4
File Size	418292
File Format	PDF
ISSN	00189200
Volume Number	26
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Programmable logic arrays Circuit faults Integrated circuit yield Circuit testing Probes Logic design Fault tolerance Manufacturing processes Very large scale integration Ultra large scale integration
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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