NDLI: An MWPC readout chip for high rate environment

Content Provider	IEEE Xplore Digital Library
Author	Kano, H. Fukunaga, C. Ikeno, M. Sasaki, O. Sato, K. Matsuura, S.
Copyright Year	1963
Abstract	An application-specified integration circuit (ASIC) has been fabricated in order to readout data from a multiwire proportional chamber (MWPC) that is installed in a high-rate environment, 16 channels and an ancillary control circuit are packed in a chip, and a channel consists of an LVDS receiver and 100-stage shift register array for delay. Hit data from the chamber is once inputted in the shift register array, and is outputted when the trigger signal is set. If a channel contains a signal during a gate followed by the trigger, the channel is regarded as containing a hit. The primary purpose for constructing the chip is for test beam and cosmic ray test of ATLAS thin gap chambers (TGC), which are used for the muon-trigger signal generation. The architecture of the ASIC is simple and independent from the specific readout scheme of ATLAS TGC. It will be found that the ASTC is adopted easily for any readout scheme of an MWPC like detector.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	509
Ending Page	513
Page Count	5
File Size	115665
File Format	PDF
ISSN	00189499
Volume Number	48
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Shift registers Pipelines Circuit testing Variable speed drives Delay Physics Signal processing Synchronization Switches
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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