NDLI: A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications

Content Provider	IEEE Xplore Digital Library
Author	Nozoe, A. Kotani, H. Tsujikawa, T. Yoshida, K. Furusawa, K. Kato, M. Nishimoto, T. Kume, H. Kurata, H. Miyamoto, N. Kubono, S. Kanamitsu, M. Koda, K. Nakayama, T. Kouro, Y. Hosogane, A. Ajika, N. Koyashi, K.
Copyright Year	1966
Abstract	A 256-Mb flash memory is fabricated with a 0.25-/spl mu/m AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm/sup 2/ die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V/sub th/. The effect of adjacent memory cell's V/sub th/ is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V/sub th/. In the -5-75/spl deg/C range, memory threshold V/sub th/ deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1544
Ending Page	1550
Page Count	7
File Size	642707
File Format	PDF
ISSN	00189200
Volume Number	34
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flash memory Threshold voltage Latches Decoding Degradation Temperature dependence Costs Equivalent circuits Throughput Semiconductor device measurement
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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