NDLI: Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Wen-Chin Lee Ya-Chin King Tsu-Jae King Chenming Hu
Copyright Year	1980
Abstract	Poly-Si/sub 1-x/Ge/sub x/-gated MOS capacitors were fabricated with x varying from 0 to 0.5. NMOS and PMOS C-V characteristics were measured. Reduced poly-gate depletion effect (PDE) was observed in PMOS devices with increasing Ge mole fraction; while for NMOS, devices with a Ge content /spl sim/20% exhibit the least PDE. Higher active dopant concentration and reduced gate-depletion width for devices featuring less PDE were confirmed. Work function difference (/spl Phi//sub MS/) was found to decrease slightly in N/sup +/ films and significantly in P/sup +/ films as Ge content increases. The shift in /spl Phi//sub MS/ for N/sup +/ poly-Si/sub 1-x/Ge/sub x/ is negligible while it is -0.13 V for P/sup +/Si/sub 0.8/Ge/sub 0.2/ and -0.32 V for P/sup +/Si/sub 0.5/Ge/sub 0.5/. The reduction in energy bandgap (/spl Delta/E/sub g/) was also determined to increase from 0 to 0.26 eV as Ge content increases from 0 to 50%. For deep submicron dual-gate CMOS application, the shift in /spl Phi//sub MS/ should be minimized for low and symmetrical V/sub th/ as well as improved short-channel effect (SCE). A Ge content of /spl sim/20% therefore seems to offer the best tradeoff between SCE and PDE.
Sponsorship	IEEE Electron Devices Society
Starting Page	247
Ending Page	249
Page Count	3
File Size	102257
File Format	PDF
ISSN	07413106
Volume Number	19
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology MOS devices Semiconductor films Implants Boron Temperature Annealing MOS capacitors Photonic band gap Threshold voltage
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimized poly-Si/sub 1-x/Ge/sub x/-gate technology for dual gate CMOS application

Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices

A variable-work-function polycrystalline-Si/sub 1-x/Ge/sub x/ gate material for submicrometer CMOS technologies

A novel p+ Poly-SiGe Gate CMOS device

Work function of boron-doped polycrystalline Si/sub x/Ge/sub 1-x/ films

Gate current and oxide reliability in p/sup +/ poly MOS capacitors with poly-Si and poly-Ge/sub 0.3/Si/sub 0.7/ gate material

Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology

Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices

Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology

Similar Documents

Optimized poly-Si/sub 1-x/Ge/sub x/-gate technology for dual gate CMOS application

Observation of reduced boron penetration and gate depletion for poly-Si/sub 0.8/Ge/sub 0.2/ gated PMOS devices

A variable-work-function polycrystalline-Si/sub 1-x/Ge/sub x/ gate material for submicrometer CMOS technologies

A novel p+ Poly-SiGe Gate CMOS device

Work function of boron-doped polycrystalline Si/sub x/Ge/sub 1-x/ films

Gate current and oxide reliability in p/sup +/ poly MOS capacitors with poly-Si and poly-Ge/sub 0.3/Si/sub 0.7/ gate material

Impact of nitrogen (N/sub 14/) implantation into polysilicon gate on high-performance dual-gate CMOS transistors

Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology

Electrical characteristics of TaSi/sub x/N/sub y/ gate electrodes for dual gate Si-CMOS devices

Investigation of poly-Si/sub 1-x/Ge/sub x/ for dual-gate CMOS technology