NDLI: High-speed CMOS continuous-time complex graphic equalizer for magnetic recording

Content Provider	IEEE Xplore Digital Library
Author	Park, J.C. Carley, L.R.
Copyright Year	1966
Abstract	A high-speed continuous-time CMOS analog adaptive equalizer for use in magnetic recording read channels is presented. The equalizer is implemented as the summation of several bandpass filters covering different frequency bands as in a graphic equalizer. The outputs from each filter are weighted by a complex coefficient and summed, which results in a linear combiner structure guaranteed to converge under least mean square (LMS) adaptation. System-level simulations of our "complex graphic equalizer (CGE)" show that its performance is comparable to that of a ten-tap finite impulse response (FIR) equalizer following a fourth-order low-pass filter when tested with two different sequence detectors: EPR4-MLSD and fixed delay tree search with decision feedback (FDTS/DF). A five-band tunable CGE has been fabricated using a 0.8-/spl mu/m CMOS technology. The highest band of the fabricated CGE was centered at 80 MHz (corresponding to channel data rate of about 200 Msymbols/s). Measured dynamic range was 68 dB, and measured total harmonic distortion was only -75 dB while consuming 97 mW at 3.3 V. The measured CGE performance agreed within 0.2 dB with the simulation results for an FDTS/DF system with an ideal CGE operating at 2.5 user bits/PW50.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	427
Ending Page	438
Page Count	12
File Size	332826
File Format	PDF
ISSN	00189200
Volume Number	33
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics Finite impulse response filter Distortion measurement Band pass filters CMOS technology Adaptive equalizers Magnetic recording Frequency Magnetic separation Nonlinear filters
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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