NDLI: A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications

Content Provider	IEEE Xplore Digital Library
Author	Jind-Yeh Lee Huan-Chang Liu Samueli, H.
Copyright Year	1966
Abstract	A very large scale integration (VLSI) implementation of an integrated adaptive beamforming processor and quadrature amplitude modulation (QAM) demodulator which will be incorporated into a frequency-hopped spread spectrum portable receiver for 2.4-GHz industrial, scientific, and medical (ISM) band applications is presented. The chip performs coherent QAM demodulation of variable constellation size and complete adaptive beamforming processing including four-channel adaptive beamforming combining, a fully programmable training processor, a readable/writable system control processor, an acquisition state machine, and a microcontroller interface. Interleaving area intensive blocks such as the 49-tap square-root Nyquist filters and 12/spl times/12 b multipliers is employed to reduce chip area. This chip can operate as a stand-alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for high bit rate indoor wireless applications. The core area of the chip is 6.22 mm/spl times/4.58 mm in 0.8-/spl mu/m CMOS technology, and the power dissipation is 610 mW at 5 V and a 5 MBaud symbol rate. In a 2.2-dB signal-to-interference-and-noise ratio environment, the receiver chip achieves a link quality of 32.6 dB SNR by performing digital adaptive beamforming to null out interferers.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	367
Ending Page	377
Page Count	11
File Size	215487
File Format	PDF
ISSN	00189200
Volume Number	33
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Array signal processing Quadrature amplitude modulation Demodulation Digital integrated circuits Very large scale integration Programmable control Adaptive control CMOS technology Frequency Spread spectrum communication
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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