NDLI: The S-LINK in the data sources for trigger demonstrators in the LHC environment

Content Provider	IEEE Xplore Digital Library
Author	Hajduk, Z. Iwariski, W. Korcyl, K. Olszowska, J. van der Bij, H.C.
Copyright Year	1963
Abstract	The hardware for the data sources to be used in the ATLAS trigger demonstrator programme has been designed and built. As a basic element, the SLATE2 module has been used. The S-LINK protocol, as a transfering data standard, has been chosen. A cheap implementation of the S-LINK, the "Parallel Electrical S-LINK", has been built. Featuring all the specification laid down in the standard it uses a parallel twisted pair copper cable as a physical layer. A standard SCSI cable has been used. Both the Source and Destination Cards have the same PCB layout. The link may receive 32-bit wide data words at max 40 MHz input rate. Running with 40 MHz link clock, it outputs 32-bit data at a rate of 20 MHz, giving total a bandwidth of 80 MB/s. We report on main characteristics of this implementation. The SLATE2SLINK card has been built to interface the SLATE motherboard to the S-LINK environment. This daughter card is capable to house and independently control 3 S-LINK sites. Running with the 25 MHZ SLATE's clock and 32-bit data, it features total a bandwidth up to 300 MB/s.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	1845
Ending Page	1848
Page Count	4
File Size	445597
File Format	PDF
ISSN	00189499
Volume Number	45
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large Hadron Collider Hardware Bandwidth Copper Clocks Detectors Physics Laboratories Throughput Optical control
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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