NDLI: A comparison of block-matching algorithms mapped to systolic-array implementation

Content Provider	IEEE Xplore Digital Library
Author	Sheu-Chih Cheng Hsueh-Min Hang
Copyright Year	1991
Abstract	This paper presents an evaluation of several well-known block-matching motion estimation algorithms from a system-level very large scale integration (VLSI) design viewpoint. Because a straightforward block-matching algorithm (BMA) demands a very large amount of computing power, many fast algorithms have been developed. However, these fast algorithms are often designed to merely reduce arithmetic operations without considering their overall performance in VLSI implementation. Three criteria are used to compare various block-matching algorithms: (1) silicon area, (2) input/output requirement, and (3) image quality. A basic systolic array architecture is chosen to implement all the selected algorithms. The purpose of this study is to compare these representative BMAs using the aforementioned criteria. The advantages/disadvantages of these algorithms in terms of their hardware tradeoff are discussed. The methodology and results presented provide useful guidelines to system designers in selecting a BMA for VLSI implementation.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	741
Ending Page	757
Page Count	17
File Size	480581
File Format	PDF
ISSN	10518215
Volume Number	7
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Motion estimation Very large scale integration Signal processing algorithms Algorithm design and analysis Hardware Costs Arithmetic Systolic arrays Circuits Silicon
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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