NDLI: Cache memories for dataflow systems

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Cache memories for dataflow systems

Content Provider	IEEE Xplore Digital Library
Author	Hurson, A.R. Kavi, K.M. Shirazi, B. Lee, B.
Copyright Year	1993
Abstract	The dataflow model of computation, particularly the recent trend in combining dataflow processing with control flow processing, provides attractive alternatives for designing new computer architectures. This marriage has also motivated researchers to analyze how to apply the familiar concepts within the framework of this new architectural model. The concept of cache memory has proven its effectiveness in the traditional control flow architecture because of the spatial and temporal localities that govern the organization of the conventional programming environment. Therefore, the authors investigate the presence of localities in dataflow programs and analyze whether the cache can be incorporated into dataflow architectures. Addressing the application of cache memory in the dataflow environment, the authors compare the control flow and dataflow programming environments, address previous work to incorporate cache in the dataflow computation, and discuss how to improve and detect locality in a dataflow program.
Starting Page	50
Ending Page	64
Page Count	15
File Size	3040800
File Format	PDF
ISSN	10636552
Volume Number	4
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-01-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Parallel processing Concurrent computing Processor scheduling Computer architecture Hardware Control systems Application software Transistors
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Computational Theory and Mathematics Electrical and Electronic Engineering

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