NDLI: A 250-MHz skewed-clock pipelined data buffer

Content Provider	IEEE Xplore Digital Library
Author	Heshami, M. Wooley, B.A.
Copyright Year	1966
Abstract	A synchronous dual-port memory employing a three-transistor (3T) dynamic cell has been designed for use as a high throughput embedded data buffer in digital switching and signal processing applications. Skewed-clock pipelining is used to achieve operation at frequencies as high as 250 MHz with a low register element count. The 3T cell provides separate read and write access ports while occupying less than half the area of a conventional dual-port SRAM cell. On-chip Hamming error correction coding (ECC) is used to enhance the fault tolerance of the memory, A 25-kb experimental prototype has been integrated in a 0.8-/spl mu/m CMOS technology; it occupies a die area of 3800 /spl mu/m/spl times/1600 /spl mu/m and dissipates 420 mW while operating at 250 MHz.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	376
Ending Page	383
Page Count	8
File Size	1230728
File Format	PDF
ISSN	00189200
Volume Number	31
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer buffers Error correction codes CMOS technology Signal design Throughput Digital signal processing Pipeline processing Frequency Registers Random access memory
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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