NDLI: A low-capacitance bipolar/BiCMOS isolation technology. II. Circuit performance and device self-heating

Content Provider	IEEE Xplore Digital Library
Author	Burghartz, J.N. Cifuentes, A.O. Warnock, J.D.
Copyright Year	1963
Abstract	For pt. 1 see ibid., vol. 41, no. 8, p. 1379-87 (1994). Device and circuit results from transistors fabricated with a novel bipolar isolation technology are presented and discussed. The isolation structure, called sequentially planarized interlevel isolation technology (SPIRIT), is fabricated by using a combination of selective epitaxial growth of silicon and a preferential polishing technique as the key process elements. This structural concept aims for reduced collector-substrate and collector-base capacitances, as well as a lower extrinsic base contact resistance, in a partial-SOI structure without significantly increasing the device temperature during operation. The feasibility of the isolation structure is demonstrated through ECL ring oscillators with gate delays of 23.6 ps at 0.72 mA and 47 ps at 0.23 mA. The temperature contours for SPIRIT and other bipolar isolation structures are simulated by using a finite-element method. It is shown that the capacitance versus self-heating tradeoff of SPIRIT is significantly improved over that of conventional trench or SOI isolation structures.<>
Sponsorship	IEEE Electron Devices Society
Starting Page	1388
Ending Page	1395
Page Count	8
File Size	906954
File Format	PDF
ISSN	00189383
Volume Number	41
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits Isolation technology Capacitance Temperature Bipolar transistor circuits Epitaxial growth Silicon Contact resistance Ring oscillators Delay
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization

Advanced One Micron BICMOS Technology for High Speed 256K SRAMS

Half-Terahertz SiGe BiCMOS technology

Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS

Advanced Heterojunction Bipolar Transistor for Half-THz SiGe BiCMOS Technology

BiCMOS integration of SiGe:C heterojunction bipolar transistors

Novel Bipolar Transistor Isolation Structure Using Combined Selective Epitaxial Growth and Planarization Technique

A new high-performance CMOS-compatible reduced-area bipolar transistor

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

A low-capacitance bipolar/BiCMOS isolation technology. II. Circuit performance and device self-heating

Similar Documents

A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization

Advanced One Micron BICMOS Technology for High Speed 256K SRAMS

Half-Terahertz SiGe BiCMOS technology

Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS

Advanced Heterojunction Bipolar Transistor for Half-THz SiGe BiCMOS Technology

BiCMOS integration of SiGe:C heterojunction bipolar transistors

Novel Bipolar Transistor Isolation Structure Using Combined Selective Epitaxial Growth and Planarization Technique

A new high-performance CMOS-compatible reduced-area bipolar transistor

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

A low-capacitance bipolar/BiCMOS isolation technology. II. Circuit performance and device self-heating