NDLI: Alternate memory compression schemes for modular multiplication

Content Provider	IEEE Xplore Digital Library
Author	Parhami, B. Lai, H.F.
Copyright Year	1991
Abstract	A memory compression scheme which reduces the size of the lookup tables for modular multiplication by using a new symmetry property is presented. The compression ratio for a modulus p is equal to 4 and implies a 75% savings except if p is even and small. Although this compression ratio has been achieved before, the present scheme has the advantage of simpler peripheral hardware. A further benefit is that it lends itself to additional reduction of table size by a factor of about two, for a total savings of 87%. This additional reduction requires two stages of table lookup or more complicated addressing circuits. This modification, which achieves table compression by a factor of eight, is quite attractive in applications where long sequences of multiplications are performed. It is shown that by using a multiplication algorithm based on squaring, a compression ratio of roughly p/2 is achievable with moderate hardware complexity, and two lookup steps.<>
Sponsorship	IEEE Signal Processing Society
Starting Page	1378
Ending Page	1385
Page Count	8
File Size	664553
File Format	PDF
ISSN	1053587X
Volume Number	41
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Table lookup Hardware Arithmetic Signal processing algorithms Delay Dynamic range Circuits Costs Throughput Pipelines
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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