NDLI: Optimal usage of CMOS within a BiCMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Wissel, L. Gould, E.L.
Copyright Year	1966
Abstract	The comparison of CMOS to BiCMOS often seen in the literature shows the delays of single-stage circuits driving a capacitive load, with the BiCMOS circuit exhibiting a bold advantage. This comparison is misleading, and it suggests that the highest possible performance chip design implemented in a BiCMOS technology, should use only BiCMOS circuits. When multistage circuits and chip wiring resistance are also considered, CMOS performance is found to be much closer to BiCMOS performance. CMOS circuits are shown to be preferred over BiCMOS circuits for a significant fraction of the chip nets. When nets that can afford a performance decrease are relaxed by using CMOS circuits instead of BiCMOS circuits, the CMOS fraction increases further. High usage of CMOS is desirable for area and yield considerations. Evaluations of the optimal CMOS role in future-generation BiCMOS technologies are expected to show an even larger role for CMOS.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	300
Ending Page	306
Page Count	7
File Size	554033
File Format	PDF
ISSN	00189200
Volume Number	27
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits CMOS technology Capacitance Voltage Delay Impedance FETs Chip scale packaging Wiring
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Can CMOS resist the BiCMOS challenge?

High-performance BiCMOS 100 K-gate array

A BiCMOS low-power current mode gate

Multiemitter BiCMOS CML circuits

A bootstrapped bipolar CMOS (B/sup 2/CMOS) Gate for low-voltage applications

A BiCMOS wired-OR logic

A unified theory for mixed CMOS/BiCMOS buffer optimization

Design and scaling of BiCMOS circuits

Low-voltage, low-power BiCMOS digital circuits

Optimal usage of CMOS within a BiCMOS technology

Similar Documents

Can CMOS resist the BiCMOS challenge?

High-performance BiCMOS 100 K-gate array

A BiCMOS low-power current mode gate

Multiemitter BiCMOS CML circuits

A bootstrapped bipolar CMOS (B/sup 2/CMOS) Gate for low-voltage applications

A BiCMOS wired-OR logic

A unified theory for mixed CMOS/BiCMOS buffer optimization

Design and scaling of BiCMOS circuits

Low-voltage, low-power BiCMOS digital circuits

Optimal usage of CMOS within a BiCMOS technology