NDLI: A bootstrapped bipolar CMOS (B/sup 2/CMOS) Gate for low-voltage applications

Content Provider	IEEE Xplore Digital Library
Author	Embabi, S.H.K. Bellaouar, A. Islam, K.
Copyright Year	1966
Abstract	This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B/sup 2/CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B/sup 2/CMOS to CMOS, BiNMOS, and BS-BiCMOS for sub-0.5 /spl mu/m BiCiMOS technologies. Simulation results have shown that the B/sup 2/CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B/sup 2/CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B/sup 2/CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	47
Ending Page	53
Page Count	7
File Size	683209
File Format	PDF
ISSN	00189200
Volume Number	30
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits Voltage Capacitance Inverters CMOS technology Logic gates CMOS logic circuits Delay MOSFETs Performance loss
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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