NDLI: CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

Content Provider	IEEE Xplore Digital Library
Author	Akiyama, N. Tamba, A. Wakui, Y. Kobayashi, Y.
Copyright Year	1963
Abstract	A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n/sup +/-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width W/sub B/, (and hence on f/sub Tmax/, since f/sub T/ varies as 1/W/sub B//sup 2/) and strong dependence on the effective base width W/sub B(eff)/, where W/sub B(eff)/ nearly equals the distance between the emitter and the n/sup +/ collector, d/sub E-C/. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short d/sub E-C/. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET.<>
Sponsorship	IEEE Electron Devices Society
Starting Page	948
Ending Page	951
Page Count	4
File Size	410522
File Format	PDF
ISSN	00189383
Volume Number	39
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bipolar transistors BiCMOS integrated circuits CMOS technology Silicon Delay effects Voltage MOSFET circuits Equivalent circuits Semiconductor process modeling Epitaxial layers
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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