NDLI: A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency

Content Provider	IEEE Xplore Digital Library
Author	De Man, E. Schulz, M. Haberecht, W.
Copyright Year	1966
Abstract	A digital interpolation filter chip with 32 programmable coefficients designed for baseband pulse shaping in digital microwave radio modems is presented. The chip was designed for a maximum sampling frequency of 80 MHz, under worst-case conditions. The desired throughput rate is achieved by applying a pipelined carry-save arithmetic. Although an optimized pipeline scheme was used, the chip complexity leads to a high capacitive clock load. The synchronization problems and the switching noise problems resulting from this high clock load were solved by dividing the clock system into subsystems and introducing and intended clock skew between the subsystems and by applying a power supply concept in which the global supply lines are consistently routed in a sandwich structure to create an on-chip buffer capacitance. The chip contains 160000 transistors on a silicon area of 78 mm/sup 2/. Typical samples were tested, and although they were fabricated in a moderate 1.5- mu m CMOS technology, their full logical functionality was verified for sampling frequencies of up to 220 MHz.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	435
Ending Page	439
Page Count	5
File Size	646510
File Format	PDF
ISSN	00189200
Volume Number	26
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interpolation Digital filters Clocks Microwave filters Sampling methods Frequency CMOS technology Baseband Pulse shaping methods Modems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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