NDLI: Memory system reliability improvement through associative cache redundancy

Content Provider	IEEE Xplore Digital Library
Author	Lucente, M.A. Harris, C.H. Muir, R.M.
Copyright Year	1966
Abstract	The development of a VLSI device that provides memory system self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques is described. This device isolates hard errors in system memory by writing a true and complement pattern to each system memory location. Locations from an on-chip fully associative cache are then mapped into the address space in place of faulty locations. Since substitutions take place at the memory word level, this method is more efficient than page swapping. Access to the onchip cache occurs in parallel with access to system memory, so memory access time is not increased, as it is with error detection and correction (EDAC). Analysis shows that this device can extend the mission time of a nonredundant memory system by as much as 35 times.<>
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	404
Ending Page	409
Page Count	6
File Size	584150
File Format	PDF
ISSN	00189200
Volume Number	26
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reliability Redundancy Very large scale integration Built-in self-test Error correction System testing Cache memory Circuit faults Writing System-on-a-chip
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Built-in redundancy analysis for memory yield improvement

Memory system reliability improvement through associative cache redundancy

Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency

Built-in Self Testing of Embedded Memories

A built-in self-test algorithm for row/column pattern sensitive faults in RAMs

A top-down built-in self-test design in VLSI testing

An efficient comparative concurrent Built-In Self-Test technique

Design and implementation of a new symmetric Built-in Redundancy analyzer

Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip

Memory system reliability improvement through associative cache redundancy

Similar Documents

Built-in redundancy analysis for memory yield improvement

Memory system reliability improvement through associative cache redundancy

Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency

Built-in Self Testing of Embedded Memories

A built-in self-test algorithm for row/column pattern sensitive faults in RAMs

A top-down built-in self-test design in VLSI testing

An efficient comparative concurrent Built-In Self-Test technique

Design and implementation of a new symmetric Built-in Redundancy analyzer

Hierarchical Built-in Self-testing and FPGA Based Healing Methodology for System-on-a-Chip

Memory system reliability improvement through associative cache redundancy