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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Pendse, R.D. |
| Copyright Year | 1978 |
| Abstract | Integrated circuit device failures induced by package stress are classifiable into two broad categories: those involving device parametric shifts resulting from the piezoresistive properties of silicon; and those involving permanent damage to interconnect features such as metal, dielectric, and passivation layer. The relevance of one or both of these failure modes to different device types is considered. The design and use of suitable test chips to address such failure modes is discussed. The application of the finite element modeling (FEM) technique to analyze package stress is demonstrated. An approach involving the combination of FEM with empirical test chip data to considerably enhance the predictive capability of FEM is presented.< |
| Sponsorship | IEEE Electronic Industries Alliance American Society of Mechanical Engineering (ASME) NBS SAE |
| Starting Page | 870 |
| Ending Page | 873 |
| Page Count | 4 |
| File Size | 334249 |
| File Format | |
| ISSN | 01486411 |
| Volume Number | 14 |
| Issue Number | 4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-12-01 |
| Publisher Place | U.S.A. |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Testing Piezoresistance Electronic packaging thermal management Thermal stresses Temperature sensors Failure analysis Silicon Passivation Surface resistance Integrated circuit interconnections |
| Content Type | Text |
| Resource Type | Article |
| Subject | Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Engineering Electrical and Electronic Engineering |
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