NDLI: Some complexity issues in digital signal processing

Content Provider	IEEE Xplore Digital Library
Author	Cappello, P. Steiglitz, K.
Copyright Year	1974
Abstract	Over the past decade a large class of problems, called NP-complete [5], have been shown to be equivalent in the sense that if a fast algorithm can be found for one, fast algorithms can be found for all. At the same time, despite much effort, no fast algorithms have been found for any, and these problems are widely regarded as intractable. This class includes such notoriously difficult problems as the traveling salesman problem, graph coloring, and satisfiability of Boolean expressions. Using FIR filter implementation as an illustration, we describe some problems in digital signal processing that are NP-complete. These include: 1) minimize the number of additions needed to implement a fixed FIR filter; 2) minimize the number of registers needed to implement a fixed FIR filter; and 3) minimize the time to perform the additions of such an FIR filter using P adders. Large-seale instances of such problems may become important with the use of programmable chips to implement signal processing. Our main purpose in this paper is to illustrate the usefulness of asymptotic complexity theory in the field of digital signal processing. The theory discriminates between tractable and intractable problems, Sometimes identifies fast algorithms for the former, and justifies heuristics for the latter.
Starting Page	1037
Ending Page	1041
Page Count	5
File Size	639689
File Format	PDF
ISSN	00963518
Volume Number	32
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1984-10-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Signal processing algorithms Finite impulse response filter Digital signal processing chips Polynomials Registers Adders Large-scale systems Complexity theory Design optimization
Content Type	Text
Resource Type	Article
Subject	Signal Processing

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimization of one-bit full adders embedded in regular structures

A 100 MHz 40-tap programmable FIR filter chip

Automated design of low complexity FIR filters

A VLSI implementation of residue adders

Computing minimum-phase factors of polynomials

Architecture optimization of a finite impulse response filter using toggle-based power estimation

Interior-Point Algorithms for Sum-Of-Squares Optimization of Multidimensional Trigonometric Polynomials

Reconfigurable multiple constant multiplication using minimum adder depth

Design of low-complexity and high-speed digital Finite Impulse Response filters

Some complexity issues in digital signal processing

Similar Documents

Optimization of one-bit full adders embedded in regular structures

A 100 MHz 40-tap programmable FIR filter chip

Automated design of low complexity FIR filters

A VLSI implementation of residue adders

Computing minimum-phase factors of polynomials

Architecture optimization of a finite impulse response filter using toggle-based power estimation

Interior-Point Algorithms for Sum-Of-Squares Optimization of Multidimensional Trigonometric Polynomials

Reconfigurable multiple constant multiplication using minimum adder depth

Design of low-complexity and high-speed digital Finite Impulse Response filters

Some complexity issues in digital signal processing