NDLI: A limitation of channel length in dynamic memories

Content Provider	IEEE Xplore Digital Library
Author	Nishizawa, J. Ohmi, T. Hsiao-Liang Chen
Copyright Year	1963
Abstract	Effects of the channel length on the memory retention characteristics of MOS dynamic RAM (dRAM) cell are studied experimentally by evaluating three different n⁺polysilicon-gate n-channel samples which contain six different channel lengths. A marked decrease of the memory holding time, which results from the subthreshold current, has been observed with decreasing channel length, gate oxide thickness, and substrate doping density in these n-channel samples with n⁺polysilicon gate. In an n-channel structure with p⁺polysilicon gate, the surface potential of the channel increases thus suppressing the surface subthreshold current particularly in a device having a thin oxide layer. A p⁺polysilicon-gate n-channel dRAM cell having an effective channel length of 0.5 µm has been observed to hold its charge up to 96 s at room temperature for the substrate bias of-4 V, while the n⁺polysilicon-gate n-channel dRAM cell having the same structure exhibits a memory holding time of 6 ms at the same substrate bias voltage. This paper introduces a new dynamic RAM cell, i.e., the p⁺polysilicon-gate n-channel cell having a buried p⁺region along the channel and the storage region. This new device having an effective channel length of 0.2 µm has been demonstrated theoretically to show satisfactory retention characteristics. In this very-short-channel structure, the MOS transistor behaves as a MOSSIT. In addition, it has been demonstrated theoretically that the new dynamic RAM cell has the capability of reducing soft errors due to alpha-particle irradiation.
Sponsorship	IEEE Electron Devices Society
Starting Page	1640
Ending Page	1649
Page Count	10
File Size	920531
File Format	PDF
ISSN	00189383
Volume Number	27
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1980-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

New self-adjusted dynamic source multilevel p-channel flash memory

Alpha-particle-induced soft errors in dynamic memories

One-device cells for dynamic random-access memories: A tutorial

Dynamic data reallocation in bubble memories

Charge-density limitation in electrofluid dynamic power generation

A Limitation of Channel Length in Dynamic Memories

Erratic cell behavior in channel hot electron programming of NOR flash memories

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

MOSFET channel length: extraction and interpretation

A limitation of channel length in dynamic memories

Similar Documents

New self-adjusted dynamic source multilevel p-channel flash memory

Alpha-particle-induced soft errors in dynamic memories

One-device cells for dynamic random-access memories: A tutorial

Dynamic data reallocation in bubble memories

Charge-density limitation in electrofluid dynamic power generation

A Limitation of Channel Length in Dynamic Memories

Erratic cell behavior in channel hot electron programming of NOR flash memories

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

MOSFET channel length: extraction and interpretation

A limitation of channel length in dynamic memories