NDLI: Energy-Efficient, QoS-Aware Packet Scheduling in High-Speed Networks

Content Provider	IEEE Xplore Digital Library
Author	Qun Yu Znati, T. Wang Yang
Copyright Year	1983
Abstract	In current commercial routers, faster network processor units (NPUs) in line cards (LCs) can significantly improve network QoS performance. However, this improvement may come at a high cost of energy consumption. In this paper, we propose and investigate two classes of QoS-aware DVFS-based packet scheduling schemes. The first class uses queue length (QL) to control execution rates in line cards, whereas the second uses link utilization to achieve the same purpose. Excessive reduction in execution rate to save energy, however, may result in a sharp increase in network delay. To address this challenge, different frequency scaling strategies are proposed, and the performance of their associated schedulers is investigated. The simulation results show that both QL-aware and Load-aware DVFS have potential for significant energy saving in high-speed networks, with acceptable delay performance. Furthermore, a simulation study is carried out to compare the performance of the proposed schemes to similar schemes described in the literature for different network environments and traffic loads. The results show that the mQ̅LA scheme achieves the best results, with performance gains of up to 9.5% energy saving, while meeting the QoS performance of the supported applications.
Starting Page	2789
Ending Page	2800
Page Count	12
File Size	1462564
File Format	PDF
ISSN	07338716
Volume Number	33
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Quality of service Energy consumption Time-frequency analysis Program processors Green communications Time measurement Simulation Energy-efficient networks DPM DVFS QoSaware scheduling Network performance QoS-aware scheduling
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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