NDLI: A CMOS 77-GHz Receiver Front-End for Automotive Radar

Content Provider	IEEE Xplore Digital Library
Author	Viet Hoang Le Hoa Thai Duong Anh Trong Huynh Ta, C.M. Fan Zhang Evans, R.J. Skafidas, E.
Copyright Year	1963
Abstract	This paper presents the design of a receiver (Rx) front-end for automotive radar application operating at 76-77 GHz. The Rx employs a double conversion architecture, which consists of a five-stage low-noise amplifier (LNA), a sub-harmonic mixer (SHM), and a double-balanced passive mixer (PSM). By adopting this architecture, millimeter-wave frequency synthesizer design can be relaxed. In the LNA layout, the output of each stage is positioned close to the input of the follow stage, thus creating a LC resonance load. As a result, complex interstage matching networks is simplified. The SHM driven by a 38-GHz local oscillator (LO) is adopted to avoid push/pull effect and power consumption of the voltage-controlled oscillator. A PSM is utilized for the second conversion since it consumes no dc current and has low flickering noise. To connect the singled-ended LNA and SHM, a 77-GHz balun is designed; and for driving the SHM, two 38-GHz baluns and an in-phase/quadrature coupler to provide quadrature 38-GHz LO are designed. The proposed Rx is implemented in a 65-nm CMOS technology and measurement results show 16-dB voltage gain and 13-dB calculated noise figure while dissipating 23.5 mA from a black 1.2-V supply.
Sponsorship	IEEE Microwave Theory and Techniques Society
Starting Page	3783
Ending Page	3793
Page Count	11
File Size	2412005
File Format	PDF
ISSN	00189480
Volume Number	61
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Radar Mixers Gain CMOS integrated circuits Impedance matching Impedance sub-harmonic mixer (SHM) Balun in-phase/quadrature (IQ) coupler low-noise amplifier (LNA) passive mixer (PSM) receiver (Rx) front-end 77-GHz CMOS radar
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering Radiation

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design and Analysis of a 21–29-GHz Ultra-Wideband Receiver Front-End in 0.18-$mu$ m CMOS Technology

Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network

A 2G/3G/4G SAW-Less Receiver Front-End Adopting Switchable Front-End Architecture

A 0.46-mm$ ^{2}$ 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

Compact and high-linearity 77 GHz CMOS receiver front-end for automotive radar

A 250 mV, 352 $mu$W GPS Receiver RF Front-End in 130 nm CMOS

A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique

Ultra-wideband wireless receiver front-end for high-speed indoor applications

A CMOS 77-GHz Receiver Front-End for Automotive Radar

Similar Documents

Design and Analysis of a 21–29-GHz Ultra-Wideband Receiver Front-End in 0.18-$mu$ m CMOS Technology

Design of 24-GHz High-Gain Receiver Front-End Utilizing ESD-Split Input Matching Network

A 2G/3G/4G SAW-Less Receiver Front-End Adopting Switchable Front-End Architecture

A 0.46-mm$ ^{2}$ 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

Compact and high-linearity 77 GHz CMOS receiver front-end for automotive radar

A 250 mV, 352 $mu$W GPS Receiver RF Front-End in 130 nm CMOS

A 0.6-V 0.33-mW 5.5-GHz Receiver Front-End Using Resonator Coupling Technique

Ultra-wideband wireless receiver front-end for high-speed indoor applications

A CMOS 77-GHz Receiver Front-End for Automotive Radar