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A set-associative, fault-tolerant cache design
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Lamet, Dan Frenzel, James F. |
| Copyright Year | 1992 |
| Description | The design of a defect-tolerant control circuit for a set-associative cache memory is presented. The circuit maintains the stack ordering necessary for implementing the Least Recently Used (LRU) replacement algorithm. A discussion of programming techniques for bypassing defective blocks is included. |
| File Size | 376411 |
| Page Count | 5 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19940017258 |
| Archival Resource Key | ark:/13960/t7wm66d04 |
| Language | English |
| Publisher Date | 1992-01-01 |
| Access Restriction | Open |
| Subject Keyword | Computer Programming And Software Integrated Circuits Chips Memory Devices Fault Tolerance Algorithms Architecture Computers Instruction Sets Computers Error Correcting Codes Computer Storage Devices Memory Computers Defects Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Article |
