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A high speed ccsds encoder for space applications
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Liu, K. Whitaker, S. |
| Copyright Year | 1990 |
| Description | This paper reports a VLSI implementation of the CCSDS standard Reed Solomon encoder circuit for the Space Station. The 1.0 micron double metal CMOS chip is 5.9 mm by 3.6 mm, contains 48,000 transistors, operates at a sustained data rate of 320 Mbits/s, and executes 2,560 Mops. The chip features a pin selectable interleave depth of 1 to 8. Block lengths of up to 255 bytes, as well as shortened codes, are supported. The control circuitry uses register cells which are immune to Single Event Upset. In addition, the CMOS process used is reported to be tolerant of over 1 Mrad total dose radiation. |
| File Size | 580543 |
| Page Count | 9 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19940004345 |
| Archival Resource Key | ark:/13960/t52g2n045 |
| Language | English |
| Publisher Date | 1990-11-06 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Radiation Hardening Radiation Effects Single Event Upsets Very Large Scale Integration Transistor Circuits Radiation Dosage Cmos Space Stations Reed-solomon Codes Coders Rates Per Time Space Communication Chips Electronics Pins Transistors Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Article |
