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A vlsi single chip (255,223) reed-solomon encoder with interleaver
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Reed, I. S. Deutsch, L. J. Truong, T. K. Hsu, I. S. |
| Copyright Year | 1987 |
| Description | A single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp. |
| File Size | 1550516 |
| Page Count | 7 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19870014399 |
| Archival Resource Key | ark:/13960/t4km4623q |
| Language | English |
| Publisher Date | 1987-05-15 |
| Access Restriction | Open |
| Subject Keyword | Electronics And Electrical Engineering Downlinking Coding Data Compression Very Large Scale Integration Chips Electronics Decoding Concatenated Codes Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Article |
