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A polymorphic reconfigurable emulator for parallel simulation
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Parrish Jr., E. A. McVey, E. S. Cook, G. |
| Copyright Year | 1980 |
| Description | Microprocessor and arithmetic support chip technology was applied to the design of a reconfigurable emulator for real time flight simulation. The system developed consists of master control system to perform all man machine interactions and to configure the hardware to emulate a given aircraft, and numerous slave compute modules (SCM) which comprise the parallel computational units. It is shown that all parts of the state equations can be worked on simultaneously but that the algebraic equations cannot (unless they are slowly varying). Attempts to obtain algorithms that will allow parellel updates are reported. The word length and step size to be used in the SCM's is determined and the architecture of the hardware and software is described. |
| File Size | 2612166 |
| Page Count | 89 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19800016517 |
| Archival Resource Key | ark:/13960/t9d55fp2x |
| Language | English |
| Publisher Date | 1980-04-01 |
| Access Restriction | Open |
| Subject Keyword | Computer Operations And Hardware Algorithms Microprocessors Arithmetic and Logic Units Architecture Computers Parallel Processing Computers Flight Simulation Real Time Operation Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
