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Memory interface simulator: a computer design aid
| Content Provider | NASA Technical Reports Server (NTRS) |
|---|---|
| Author | Williams, T. Weatherbee, J. E. Taylor, D. S. |
| Copyright Year | 1972 |
| Description | Results are presented of a study conducted with a digital simulation model being used in the design of the Automatically Reconfigurable Modular Multiprocessor System (ARMMS), a candidate computer system for future manned and unmanned space missions. The model simulates the activity involved as instructions are fetched from random access memory for execution in one of the system central processing units. A series of model runs measured instruction execution time under various assumptions pertaining to the CPU's and the interface between the CPU's and RAM. Design tradeoffs are presented in the following areas: Bus widths, CPU microprogram read only memory cycle time, multiple instruction fetch, and instruction mix. |
| File Size | 699491 |
| Page Count | 25 |
| File Format | |
| Alternate Webpage(s) | http://archive.org/details/NASA_NTRS_Archive_19730002458 |
| Archival Resource Key | ark:/13960/t7jq5r365 |
| Language | English |
| Publisher Date | 1972-10-06 |
| Access Restriction | Open |
| Subject Keyword | Airborne/spaceborne Computers Central Processing Units Multiprogramming Digital Simulation Random Access Memory Ntrs Nasa Technical Reports Server (ntrs) Nasa Technical Reports Server Aerodynamics Aircraft Aerospace Engineering Aerospace Aeronautic Space Science |
| Content Type | Text |
| Resource Type | Technical Report |
