Loading...
Please wait, while we are loading the content...
Similar Documents
Delay Fault Modelling/Simulation using VHDL-AMS in Multi-Vdd Systems
| Content Provider | CiteSeerX |
|---|---|
| Author | Ahmadi, A. Ali, N. B. Zain |
| Abstract | Abstract — With the growing density of Very Large Scale Integrated(VLSI) circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accu-rate simulations at transistor level, as in SPICE and fast simulation at gate level using a Hardware Descriptive Language (HDL) can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results. I. |
| File Format | |
| Access Restriction | Open |
| Content Type | Text |
