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Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation
| Content Provider | Semantic Scholar |
|---|---|
| Author | Kilic, Yakup Zwolinski, Mark |
| Copyright Year | 2004 |
| Abstract | One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits. |
| Starting Page | 177 |
| Ending Page | 190 |
| Page Count | 14 |
| File Format | PDF HTM / HTML |
| DOI | 10.1023/B:ALOG.0000024065.22617.5a |
| Alternate Webpage(s) | https://page-one.springer.com/pdf/preview/10.1023/B:ALOG.0000024065.22617.5a |
| Alternate Webpage(s) | https://eprints.soton.ac.uk/259464/1/5268694-KILIC.pdf |
| Alternate Webpage(s) | https://doi.org/10.1023/B%3AALOG.0000024065.22617.5a |
| Volume Number | 39 |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
