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Potentials of Chip-Package Co-Design for High-Speed Digital Applications
| Content Provider | CiteSeerX |
|---|---|
| Abstract | The inherent potentials of the Si technology are limited by the low interaction with packaging. Co-design as the symbiosis between the ICs and appropriate high-density packaging offers lower RC line delay, improved SSN and lower costs compared to single-chip approaches. The distribution of the system functionality between IC and the packaging level opens up new vistas in future electronic design and system architecture. 1. Roadmaps and co-design approach The SIA roadmap for semiconductors [1] shows an undiminished performance increase of the inherent Si device technology over the next decade. But the overall system performance depends also on the packaging as the interconnect to the system environment. A low interaction between IC and packaging design will more and more limit the system potentials. The novel chip-package co-design approach with the objective of exploiting the synergism of ICs and packaging through their concurrent and matched design is clearly focused on system-level. For the challanges in high-speed digital design, clock delay, memory bandwidth, signal switching noise and cost/performance the co-design approach offers attractive solutions. 1.1 On-chip delay The maximal clock speed is determined by the signal delay and clock skew. Signal delay is composed of the gates and the interconnect delay. Scaling of the MOS technology over the last two decades has continuously decreased the gate delay whereas the RC line delay is increasing because of the reduced line cross-section. Up to now the gate delay has dominated the delay in high-speed digital circuits. Below the 130nm technology the on-chip interconnect delay becomes more and more dominant., even if using copper (Cu) as interconnect material instead of aluminum (Figure 1). The package wiring layers provide about 1000 times less wire resistance and about 10 times less wire capacitance. Wiring of long interconnections like the global clock tree can benefit from the lower RC delay if interconnection is performed off-chip as depicted in Figure 2. |
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