Very compact FPGA implementation of the AES algorithm (2003)

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Encryption Standard Algorithm-128 using Verilog

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An fpga design of aes encryption circuit with 128-bit keys (2005).

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FPGA IMPLEMENTATION OF ENCRYPTION AND DECRYPTION ALGORITHM BASED ON AES Shivaraj.G.Nandeni

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A Compact 32-bit Architecture for an AES System

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Compact fpga implementation of camellia.

FPGA IMPLEMENTATION OF A COMPACT AES ALGORITHM WITH S-BOX OPTIMIZATION

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Aes-128 bit algorithm using fully pipelined architecture for secret communication.

A compact 32-bit architecture for an aes system.

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