Loading...
Please wait, while we are loading the content...
Similar Documents
Chapter 3 Thermal and Power Delivery Challenges in 3D
| Content Provider | CiteSeerX |
|---|---|
| Author | Jain, Pulkit Zhou, Pingqiang Kim, Chris H. Sapatnekar, Sachin S. |
| Abstract | Abstract Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines solution schemes to overcome the corresponding bottlenecks. One of the primary advantages of 3D chips stems from their ability to pack circuitry more densely than in 2D. However, this increased level of integration also results in |
| File Format | |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
