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CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse
| Content Provider | CiteSeerX |
|---|---|
| Author | Janin, Lilian Edwards, Doug |
| Abstract | Abstract. In synchronous circuit design, new levels of abstraction above RTL allow the designer to model, simulate, debug and explore various architectures more efficiently than before. These are known as transaction level modeling. The translation between signals at different levels of abstraction is performed by pieces of code called transactors, mainly for the purpose of simulation. This paper identifies a set of asynchronous abstractions suitable for asynchronous transaction level modeling. Based on these models, we show that asynchronous CSP-based transactors can bring many more benefits than their synchronous counterparts, while being simpler to describe. We show how they can be used to automatically generate complex SystemC templates and hardware-software links, and automatically build network-on-chip interfaces facilitating IP reuse in embedded systems. Tools were developed after the techniques described in this paper. They are used in a case study to describe an asynchronous IP from trans-action levels to RTL, demonstrating the automatic generation of various com-plex parts of the design and the minimum amount of specifications required from the designer. 1 |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Asynchronous Transaction Level Modeling Ip Reuse Csp Transactor Hardware-software Link New Level Minimum Amount Case Study Asynchronous Abstraction Asynchronous Ip Network-on-chip Interface Various Architecture Various Com-plex Part Synchronous Circuit Design Automatic Generation Transaction Level Modeling Asynchronous Csp-based Transactor Trans-action Level Different Level Complex Systemc Template Embedded System Synchronous Counterpart |
| Content Type | Text |
| Resource Type | Article |
