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High-Level Crosstalk Defect Simulation for System-on-Chip Interconnects (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Bai, Xiaoliang Dey, Sujit |
| Description | Proc. 19 th VLSI Test Symp |
| File Format | |
| Language | English |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Long Interconnects Effective Crosstalk-defect Coverage-analysis Technique Nanometer Technology High-level Crosstalk Defect Simulation Crosstalk-defect Coverage Efficient High-level Crosstalk-defect Simulation Methodology Crosstalk Defect Timing Failure High-fidelity Defect-coverage Result Defect-simulation Model High-level Crosstalk-defect Simulation Methodology Hardware Description Capacitive Coupling Effect Low-cost Manufacturing Test System-on-chip Interconnects Crosstalk Defect Simulation Methodology Crosstalk-induced Ac Failure New Crosstalk Test Methodology Spice Simulation Experimental Result Fast Exploration Different Test Error-free Operation |
| Content Type | Text |
| Resource Type | Article |
