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Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (2002)
| Content Provider | CiteSeerX |
|---|---|
| Author | Chen, Li Bai, Xiaoliang Dey, Sujit |
| Description | Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for systemon -chips (SoC) based on embedded processors. It enables an onchip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method. 1. |
| File Format | |
| Language | English |
| Publisher Date | 2002-01-01 |
| Publisher Institution | Processor Cores,” in Proc. Design Automation Conf. (DAC’01 |
| Access Restriction | Open |
| Subject Keyword | Excessive Test Overhead On-chip Embedded Processor Core Long Interconnects New Software-based Self-test Methodology Self-test Program Defect Coverage Processor-memory System Processor Core System-level Crosstalk Defect Simulation Method High-speed Tester System-level Interconnects Normal Operational Mode Embedded Processor Interconnect Crosstalk Aggressive Testing Systemon Chip Crosstalk Effect External Testing |
| Content Type | Text |
| Resource Type | Article |
