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Wu “An integrated ECC and redundancy repair scheme for memory reliability enhancement (2005)
Content Provider | CiteSeerX |
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Author | Su, Chin-Lung Yeh, Yi-Ting Wu, Cheng-Wen |
Description | 20th IEEE International Symposium |
File Format | |
Language | English |
Publisher Date | 2005-01-01 |
Access Restriction | Open |
Subject Keyword | Memory Reliability Enhancement Integrated Ecc Hard Fault Semiconductor Memory Memory Chip Redundancy Repair Scheme Memory Reliability Memory Normal Operation Mode Repair Scheme Soft Error High Level Memory Idle Time Experimental Result Ecc Technique Deep Submicron Technology Memory Product Fast Development Pace Redundancy Repair Unused Redundant Element |
Content Type | Text |
Resource Type | Article |