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A Study on Al2O3 Deposition by Atomic Layer Deposition for III-Nitride Metal-Insulator-Semiconductor Field Effect Transistors
| Content Provider | CiteSeerX |
|---|---|
| Author | Lee, Yi-Che Kao, Tsung-Ting Shen, Shyh-Chiang |
| Abstract | Al2O3 deposited by atomic-layer deposition (ALD) technique is one of the most promising gate dielectrics for MIS devices. Several studies have revealed the impact of ALD deposition recipe and post-deposition annealing recipe to the performance of III-N metal-insulator-semiconductor (MIS) devices [1-3]. While the oxygen sources and annealing conditions have been studied, the impact of process variables and their interactions to electrical properties of MIS high electron mobility transistors (MIS-HEMTs) are still unclear. In this work, we studied six ALD Al2O3 deposition and annealing variables using a fractional factorial design of experiments and explored an optimal processing condition to achieve small threshold voltage (Vth) shift, low I-V hysteresis and low gate-to-source (GS) diode leakage current for MIS-HEMT processing. Six experimental factors (ni) for the ALD deposition and post-deposition annealing recipes were tested in this study using a custom-built ALD tool and Annealsys AS-One annealing system. 15nm-thick Al2O3 was deposited on all the samples and annealed in oxygen atmosphere. Each factor has a two-level design, designated as high level (H) and low level (L), respectively. In the designed experiment, the levels of TMA pulse time (n5) and gas dwell time (n6) are generated by the other four variables using equations of n5 = n1·n2·n3 and n6=n2·n3·n4. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Iii-nitride Metal-insulator-semiconductor Field Effect Transistor Atomic Layer Deposition Al2o3 Deposition N6 N2 N3 N4 15nm-thick Al2o3 Several Study Diode Leakage Annealsys As-one Small Threshold Voltage Iii-n Metal-insulator-semiconductor Low I-v Hysteresis Electrical Property Gas Dwell Time Promising Gate Dielectric Tma Pulse Time Six Experimental Factor Mi Device Oxygen Source Ald Al2o3 Deposition Fractional Factorial Design Mis-hemt Processing Optimal Processing Condition Custom-built Ald Tool Post-deposition Annealing Recipe Ald Deposition Recipe High Level Two-level Design Process Variable Atomic-layer Deposition Low Gate-to-source N5 N1 N2 N3 Mi High Electron Mobility Transistor Ald Deposition Low Level |
| Content Type | Text |
