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Uniprocessor virtual memory without tlbs (2001)
| Content Provider | CiteSeerX |
|---|---|
| Author | Jacob, Bruce Mudge, Trevor |
| Abstract | AbstractÐWe present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features as shared memory, superpages, fine-grained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardware-defined mechanisms. Index TermsÐVirtual memory, virtual address translation, virtual caches, memory management, software-managed address translation, translation lookaside buffers. æ 1 |
| File Format | |
| Journal | IEEE Transactions on Computers |
| Language | English |
| Publisher Date | 2001-01-01 |
| Access Restriction | Open |
| Subject Keyword | Uniprocessor Virtual Memory Software-managed Address Translation Virtual Address Translation Hardware-defined Mechanism Virtual Cache Trace-driven Simulation Fine-grained Protection Address Translation Hardware Shared Memory Processor Design Simpler Index Term Virtual Memory Address Translation Feasibility Study Sparse Address Space Hardware-managed Address Translation Specialized Translation Hardware Performance Impact Translation Lookaside Buffer Memory Management |
| Content Type | Text |
| Resource Type | Article |
