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Options for Dynamic Address Translation in COMAs (1998)
| Content Provider | CiteSeerX |
|---|---|
| Author | Qiu, Xiaogang Dubois, Michel |
| Description | In modern processors, the dynamic translation of virtual addresses to support virtual memory is done before or in parallel with the first-level cache access. As processor technology improves at a rapid pace and the working sets of new applications grow insatiably the latency and bandwidth demands on the TLB (Translation Lookaside Buffer) are getting more and more difficult to meet. The situation is worse in multiprocessor systems, which run larger applications and are plagued by the TLB consistency problem. We evaluate and compare five options for virtual address translation in the context of COMAs (Cache Only Memory Architectures). The dynamic address translation mechanism can be located after the cache access provided the cache is virtual. In a particular design, which we call V-COMA for Virtual COMA, the physical address concept and the traditional TLB are eliminated. While still supporting virtual memory, V-COMA reduces the address translation overhead to a minimum. V-COMA scales w... |
| File Format | |
| Language | English |
| Publisher | IEEE Press |
| Publisher Date | 1998-01-01 |
| Publisher Institution | In Proceedings of the 25th International Symposium on Computer Architecture (ISCA |
| Access Restriction | Open |
| Subject Keyword | Bandwidth Demand Translation Lookaside Buffer Rapid Pace Processor Technology Cache Access Modern Processor Address Translation Overhead V-coma Scale New Application Tlb Consistency Problem Virtual Memory First-level Cache Access Dynamic Translation Particular Design Virtual Address Translation Virtual Address Memory Architecture Dynamic Address Translation Mechanism Virtual Coma Dynamic Address Translation Physical Address Concept Traditional Tlb Multiprocessor System |
| Content Type | Text |
| Resource Type | Article |
