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Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Horta, Edson L. Lockwood, John W. |
| Description | This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGAs) and a tool called PARBIT, it is possible to extract a partial bitstream containing a modular component developed on one Virtex FPGA that can be placed or relocated inside another Virtex FPGAs. The methodology to obtain the BIP cores is explained, along with details about PARBIT and Virtex devices. Proc. Field Programmable Logic.2004 |
| File Format | |
| Language | English |
| Publisher Date | 2004-01-01 |
| Access Restriction | Open |
| Subject Keyword | Partial Bitstream Modular Component Generate Bitstream Intellectual Property Core Innovative Way Standard Tool Virtex Fpga Bitstream Intellectual Property Virtex Fpgas Virtex Device Bip Core Field Programmable Gate Array |
| Content Type | Text |
| Resource Type | Article |
