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SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance (2004)
| Content Provider | CiteSeerX |
|---|---|
| Author | Chin, James Nourani, Mehrdad |
| Description | We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule. |
| File Format | |
| Language | English |
| Publisher Date | 2004-01-01 |
| Publisher Institution | IEE Proceedings - Computers and Digital Techniques |
| Access Restriction | Open |
| Subject Keyword | Soc Test Schedule Power-time Tradeoff Core-based System-on-chips Soc Test Satisfy Constraint Hot Spot Mixed Integer Linear Programming Formulation Test Scheduling Methodology Physical Power Dissipation Hot Spot Avoidance Overall Test Time |
| Content Type | Text |
| Resource Type | Article |
