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Power-time tradeoff in test scheduling for socs (2003).
| Content Provider | CiteSeerX |
|---|---|
| Abstract | We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of non-embedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and produce the SoC test schedule. Many constraints including peak/average power of cores, time/sequencing requirements, and ATE pin limitation are also incorporated within this formulation. I. |
| File Format | |
| Publisher Date | 2003-01-01 |
| Access Restriction | Open |
| Subject Keyword | Soc Test Schedule Power-time Tradeoff Core-based System-on-chips Many Constraint System Power Dissipation Power Profile Basic Strategy Time Sequencing Requirement Test Scheduling Ate Pin Limitation Time Constraint Peak Average Power Test Scheduling Methodology Non-embedded Core Milp Formulation Overall Test Time Test Pattern Subset |
| Content Type | Text |
