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Advanced channel engineering achieving aggressive reduction of VT variation for ultralow-power applications (2011)
| Content Provider | CiteSeerX |
|---|---|
| Author | Miyake, T. Fujita, K. Torii, Y. Nakagawa, M. Okabe, K. Shifren, L. Oh, J. Ranade, P. Hori, M. |
| Abstract | We have achieved aggressive reduction of VT variation and VDD-min by a sophisticated planar bulk MOSFET named ‘Deeply Depleted Channel TM (DDC)’. The DDC transistor has been successfully integrated into an existing 65nm CMOS platform by combining layered channel formation and low temperature processing. The 2x reduction of VT variation in 65nm-node has been demonstrated by matching SRAM pair transistors, 2x improvement in SRAM static noise margin (SNM) and 300 mV VDD-min reduction of 576Kb SRAM macros to 0.425 V using conventional 6T cell layout. |
| File Format | |
| Journal | Proc. IEEE Int. Electron. Devices Meeting |
| Publisher Date | 2011-01-01 |
| Access Restriction | Open |
| Subject Keyword | Advanced Channel Engineering Ultralow-power Application Layered Channel Formation Sophisticated Planar Bulk Mosfet Deeply Depleted Channel Tm Ddc Transistor Cell Layout Sram Pair Transistor Aggressive Reduction Sram Static Noise Margin Low Temperature Processing Mv Vdd-min Reduction Vt Variation Cmos Platform Sram Macro |
| Content Type | Text |
