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An Approach To Low-Power, High-Performance, Fast Fourier Transform Processor Design (1999)
| Content Provider | CiteSeerX |
|---|---|
| Author | Baas, Bevan M. Baas, M. |
| Abstract | The Fast Fourier Transform (FFT) is one of the most widely used digital signal processing algorithms. While advances in semiconductor processing technology have enabled the performance and integration of FFT processors to increase steadily, these advances have also caused the power consumed by processors to increase as well. This power increase has resulted in a situation where the number of potential FFT applications limited by maximum power budgets not performance is signicant and growing. We present the cached-FFT algorithm which explicitly caches data from main memory using a much smaller and faster memory. This approach facilitates increased performance and, by reducing communication energy, increased energy-eÆciency. Spiee is a 1024-point, single-chip, 460,000-transistor, 40-bit complex FFT processor designed to operate at very low supply voltages. It employs the cached-FFT algorithm which enables the design of a well-balanced, nine-stage pipeline. The processor calculates a c... |
| File Format | |
| Publisher Date | 1999-01-01 |
| Access Restriction | Open |
| Subject Keyword | Digital Signal Processing Algorithm Power Increase Semiconductor Processing Technology Energy-e Ciency Communication Energy 40-bit Complex Fft Processor Fast Fourier Transform Processor Design Maximum Power Budget Fft Processor Cached-fft Algorithm Nine-stage Pipeline Potential Fft Application Increased Performance Low Supply Voltage |
| Content Type | Text |
