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A Hierarchy-Driven FPGA Partitioning Method (1997)
| Content Provider | CiteSeerX |
|---|---|
| Author | Abbara, Ali Saucier, Gabrièle Krupnova, Helena |
| Description | In 34th Design Automation Conference (DAC |
| Abstract | This paper addresses an automatic partitioning method of a design into several FPGAs. Although the circuit partitioning methods have recently been significantly advanced, partitioning is commonly performed at the gate netlist level. To cope with large designs and explore the solution space efficiently, clustering of the logic is mandatory. In this paper, the hierarchy of the design, naturally introduced by the designer, guides the partitioning. The basic concepts are introduced in terms of "envelope" delimiting hierarchy blocks. These concepts lead to an "envelope"-based clustering and to the proposed final hierarchy-driven partitioning. Results are given on industrial examples on XILINX 4000 technology. 1. Introduction Circuit partitioning consists in dividing the circuit in two or more blocks such that the number of connections between the blocks of the partition is minimized ([6], [10], [14]). The partitioning problem is NP-complete and commonly heuristic methods are used to reach... |
| File Format | |
| Publisher Date | 1997-01-01 |
| Access Restriction | Open |
| Subject Keyword | Several Fpgas Basic Concept Solution Space Partitioning Problem Hierarchy Block Hierarchy-driven Fpga Partitioning Method Introduction Circuit Final Hierarchy-driven Partitioning Large Design Heuristic Method Gate Netlist Level Automatic Partitioning Method Industrial Example |
| Content Type | Text |
| Resource Type | Conference Proceedings Article |
